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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Product Features
* External quartz oscillator 32.000kHz and 32.768kHz selectable. * Supports I2C-Bus's high speed mode (400 kHz) * Includes time (Hour/Minute/Second) and calendar (Year/Month/Date/Day) counter functions (BCD code) * Select between 12-hr and 24-hr clock display * Auto calculation of leap years until 2099 * Built-in high-precision clock precision control logic * Interrupt generation function (cycle time range: 1 month to 0.5 seconds, includes interrupt flags and interrupt stop function) * Alarm functions (Alarm_A/B: Day/Hour/Min) * 32-kHz clock output (PT7C4372B: FOUT output; PT7C4372A: /INTB output) * Oscillation stop detection function (used to determine presence of internal data)
* Wide clock voltage range: 1.45 V to 6 V
Product Description
PT7C4372A/B are I2C bus interface-compliant real-time clocks that have been adjusted for high precision. In addition to providing a function for generating six types of interrupts, a dual alarm function, an oscillation stop detection function (used to determine presence of valid internal data at power-on), they includes a digital clock precision adjustment function that can be used to set various levels of precision. Since the internal oscillation circuit is driven at a constant voltage, 32-kHz clock output is stable and free of voltage fluctuation effects. Table 1 shows the diverse functions of the two RTC circuits. More details are shown in section Overview of Functions.
Ordering Information
Part Number PT7C4372AL PT7C4372BL PT7C4372AW PT7C4372BW Package 8-Pin TSSOP 8-Pin TSSOP 8-Pin SOP 8-Pin SOP
* Wide interface voltage range: 2 V to 6 V * Low current consumption: 0.5 A/3.0 V (Typ.)
Note: Lead free package is available by adding "E" after part no. For example: PT7C4372ALE is the lead free package of PT7C4372AL. Table 1. Diverse functions of RTC circuits Item 1 2 3 4 5 6 7 8 Function Clock Clock adjustment Period interrupt Alarm Oscillation detect 32-kHz clock output I2C bus interface with CPU Crystal PT7C4372A Unit 3.051ppm for 32.768kHz crystal; 3.125ppm for 32.000kHz crystal Output from /INTA and /INTB /INTA: Alarm_A; /INTB: Alarm_B via /INTB enabled by register External, 32.768kHz or 32.000kHz selectable PT7C4372B Same as PT7C4372A Output from /INTA /INTA: Alarm_A or Alarm_B via FOUT enable by register Same as PT7C4372A
PT0150(03/06) 1
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Contents
Product Features ************************************************************************************************************************************************************* 1 Product Description******************************************************************************************************************************************************** 1 Pin Assignment*************************************************************************************************************************************************************** 3 Pin Description *************************************************************************************************************************************************************** 3 Function Block *************************************************************************************************************************************************************** 4 Function Description ****************************************************************************************************************************************************** 5 Overview of Functions ******************************************************************************************************************************************* 5 Clock function************************************************************************************************************************************************* 5 Clock precision adjustment function*************************************************************************************************************** 5 Periodic interrupt ******************************************************************************************************************************************** 5 Alarm function ************************************************************************************************************************************************ 5 Oscillation stop detection function, power drop detection function ***************************************************************5 (voltage monitoring function), and power-on reset detection function 32-kHz clock output**************************************************************************************************************************************** 5 Registers ***************************************************************************************************************************************************************** 6 Allocation of Registers *********************************************************************************************************************************** 6 Register 1 ******************************************************************************************************************************************************** 7 Register 2 ******************************************************************************************************************************************************** 8 Time Counter ************************************************************************************************************************************************** 9 Days of the Week Counter ****************************************************************************************************************************** 10 Calendar Counter ******************************************************************************************************************************************** 10 Time Trimming Register********************************************************************************************************************************* 10 Alarm Register ************************************************************************************************************************************************ 11 Clock Precision Adjustment Function ******************************************************************************************************************** 12 Alarm Function******************************************************************************************************************************************************* 13 Periodic Interrupt Function************************************************************************************************************************************* 16 Various Detection Function************************************************************************************************************************************ 19 Reading / Writing Data via the I2C Bus Interface*************************************************************************************************** 20 Overview of I2C-BUS ************************************************************************************************************************************* 20 System Configuration ************************************************************************************************************************************* 20 Starting and Stopping I2C Bus Communications ******************************************************************************************* 21 Data Transfers and Acknowledge Responses during I2C-BUS Communication******************************************** 22 Slave Address************************************************************************************************************************************************** 23 Configuration of Oscillating Circuit and Timing Trimming ****************************************************************************************** 26 Specifications ***************************************************************************************************************************************************************** 28 Recommended Operating Conditions********************************************************************************************************************* 28 Frequency Characteristics*************************************************************************************************************************************** 28 DC Electrical Characteristics********************************************************************************************************************************** 29 AC Electrical Characteristics********************************************************************************************************************************** 30 Mechanical Information ************************************************************************************************************************************************* 31 L/LE (8-pin TSSOP) ********************************************************************************************************************************************** 31 W/WE (8-pin SOP) ************************************************************************************************************************************************* 32 Notes******************************************************************************************************************************************************************************* 33
PT0150(03/06) 2 Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Pin Assignment
PT7C4372A
1
PT7C4372B
8 1
INTB SCL SDA GND
Vcc OSCIN OSCOUT INTA
FOUT SCL SDA GND
Vcc OSCIN OSCOUT INTA
8
2
7
2
7
3
6
3
6
4
5
4
5
8 pin TSSOP 8 pin SOP
8 pin TSSOP 8 pin SOP
Pin Description
Pin 4372 A B 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 Pin Name /INTB FOUT SCL SDA GND Type O O I I/O P O O I P Description Interrupt B (Open Drain). It outputs alarm interrupts and periodic interrupts. Oscillating Clock Output (CMOS). It can be disabled by a command from CPU. Serial Clock Line. It is for I2C communication. Data input and output across SDA pin is synchronized with this clock. Up to 6V beyond Vcc may be input. Serial Data Line (Open Drain output). This line is for transferring I2C bus format data. When input, up to 6V beyond VCC may be used. When output, it is an open drain output pin. Ground Interrupt A (Open Drain). It outputs alarm interrupts and periodic interrupts. Oscillator Circuit Output. Together with OSCIN, an crystal oscillator is connected between them. Oscillator Circuit Input. See OSCOUT pin description. Power
/INTA OSCOUT OSCIN Vcc
PT0150(03/06) 3
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Function Block
Comparator_A FOUT
(PT7C4372B only)
Alarm_A Register (Week,Min,Hour) Alarm_B Register (WEEK,MIN,HOUR)
32kHz Output Control Comparator_B
OSCIN
CD
OSC
Divider Correction
Div
Time Counter (Sec,Min,Hour,Day,Date,Month,Year)
OSCOUT
CG
OSC Detect
Address Decoder
Address Register I /O Control
SCL
/INTA
(PT7C4372A only)
Interrupt Control
Shift Register
/INTB
SDA
PT0150(03/06) 4
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Function Description
Overview of Functions
Clock function CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2099. Clock precision adjustment function They have two internal oscillation circuit capacitors, so that an oscillation circuit may be configured simply by externally connecting a crystal. Either 32.768kHz or 32.000kHz crystal may be selected to setting the internal register appropriately. The clock precision can be adjusted forward or back in units of 3.051 ppm (32.768kHz crystal) or 3.125 ppm (32.000kHz crystal) and oscillation frequency can be adjusted in 189 ppm (32.768kHz crystal) or 194 ppm (32.000kHz crystal). This function can be used to implement a higher-precision clock function, such as by: * Enabling higher clock precision throughout the year by taking seasonal clock precision adjustments into account in advance, or * Enabling correction of temperature-related clock precision variation in systems that include a temperature detecting function. Periodic interrupt * PT7C4372A Periodic interrupts can be output via the /INTA and /INTB pins. Select among five Periodic frequency settings: 2 Hz (every 0.5 seconds), 1 Hz (every second), 1/60 Hz (every minute), 1/3600Hz (every hour), or monthly. Select among two output waveforms for periodic interrupts: ordinary pulse waveform (2 Hz or 1 Hz) or waveforms (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts. A polling function is also provided to enable monitoring of pin states via registers.
*
Alarm function * PT7C4372A This module is has two alarm system (Alarm_A and Alarm_B) that outputs interrupt signals from /INTA or /INTB to CPU when the day of the week, hour or minute corresponds to the setting. Each of them may output interrupt signal separately at a specified time. The alarm may be selectable between on and off for each day of the week, thus allowing outputting alarm everyday or on a specific day of the week. The Alarm_A is output from the /INTA pin while the Alarm_B is output from either the /INTA or the /INTB pins. Polling is possible separately for each alarm function.
*
PT7C4372B This module is equipped with two alarm functions (Alarm_A and Alarm_B) that output interrupt signals from /INTA to the host when to day of the week, hour or minute corresponds to the setting. The alarm may be selectable between on and off for each day of the week, thus allowing outputting alarm everyday or on a specific day of the week. Polling is possible separately for each alarm function. Oscillation stop detection function, power drop detection function (voltage monitoring function), and power-on reset detection function PT7C4372A/B have only oscillation stop detection function. The oscillation stop detection function uses registers to record if clock data is valid or invalid. This function may be used to determine if the PT7C4372A/B supply power has been booted from 0V and if it has been backed up.
Interface with CPU Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since the output of the I/O pin of SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is also open drain. The SCL's maximum clock frequency is 400 kHz, which supports the I2C bus's high-speed mode. 32-kHz clock output The 32.768 kHz clock (32.768kHz crystal) or 32.000kHz clock (32.000kHz crystal) can be output via the /INTB (only PT7C4372A) or FOUT (only PT7C4372B) pin by setting corresponding register. Note: The precision of this 32.768 kHz clock output via the FOUT pin can not be adjusted (even when using the clock precision adjustment function).
PT7C4372B Periodic interrupts can be output via the /INTA pin. Select among five Periodic frequency settings: 2 Hz (every 0.5 seconds), 1 Hz (every second), 1/60 Hz (every minute), 1/3600Hz (every hour), or monthly. Select among two output waveforms for periodic interrupts: ordinary pulse waveform (2 Hz or 1 Hz) or waveforms (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts. A polling function is also provided to enable monitoring of pin states via registers. 5
PT0150(03/06)
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Registers
Allocation of registers
Addr.
0 1 2 3 4 5 6 7 8 9 A B C D E F
Function
Second Minutes Hours Days of the week Days Months Years Time Trimming Alarm_A: Minute Alarm_A: Hour Alarm_A: Day Alarm_B: Minute Alarm_B: Hour Alarm_B: Day Control 1 Control 2
Bit 7
-*5 Y80 /XSL AALE -
Bit 6
S40 M40 Y40 F6 AM40 AW6 BM40 BW6 BALE -
Bit 5
S20 M20 H20 or P, /A D20 Y20 F5 AM20 AH20 or AP, /A AW5 BM20 BH20 or BP, /A BW5 SL2*4 /12, 24
Bit 4
S10 M10 H10 D10 M10 Y10 F4 AM10 AH10 AW4 BM10 BH10 BW4 SL1*4 ADJ or XSTP*3
Bit 3
S8 M8 H8 D8 M8 Y8 F3 AM8 AH8 AW3 BM8 BH8 BW3 TEST*2 /CLEN
Bit 2
S4 M4 H4 W4 D4 M4 Y4 F2 AM4 AH4 AW2 BM4 BH4 BW2 CT2 CTFG
Bit 1
S2 M2 H2 W2 D2 M2 Y2 F1 AM2 AH2 AW1 BM2 BH2 BW1 CT1 AAFG
Bit 0
S1 M1 H1 W1 D1 M1 Y1 F0 AM1 AH1 AW0 BM1 BH1 BW0 CT0 BAFG
Caution points: *1. All bits marked with "-" are read-only bits. Their value when read is always "0". *2. The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit. *3. ADJ is for writ and XTSP is for read operation. The XTSP bit is set to "0" by writing data into the control register 2 for normal oscillation. When XSTP is set to "1", the Time Trimming register, Control 1 register, /CLEN and TEST bits are reset to "0". *4. SL1 and SL2 apply to the PT7C4372A. For the PT7C4372B, these bits must be filled with "0". *5. All bits marked with "-" are read-only bits. Their value when read is always "0".
PT0150(03/06) 6
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Control register 1 Addr. E Description Control 1 (default) D7 AALE 0 D6 BALE 0 D5 SL2 0 D4 SL1 0 D3 TEST 0 D2 CT2 0 D1 CT1 0 D0 CT0 0
SL1 and SL2 apply to the PT7C4372A. For the PT7C4372B, these bits must be filled with "0".
*
AALE, BALE Alarm_A, Alarm_B enable bits. AALE, BALE Read / Write Data 0 1 Description Alarm_A (Alarm_B) correspondence action invalid Alarm_A (Alarm_B) correspondence action valid Default
See section "Alarm Function" for more detail.
*
SL2, SL1 (PT7C4372A only) Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may be output to the /INTA or /INTB pins selectively by SL1 and SL2. SL2 0 0 1 1 SL1 0 1 0 1 TEST TEST Read / Write Data 0 1 Description Ordinary operation mode Test mode Default Description Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB. Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB. Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB. Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB. Default
*
PT0150(03/06) 7
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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CT2, CT1, CT0 Periodic interrupt output select bits. CT2 CT1 CT0 Wave Form Mode Pulse Pulse Level Level Level Level Description Cycle / Falling Timing Off ("H") Fixed at "L" 2Hz (duty 50%) 1Hz (duty 50%) Every second (synchronized with second count up) Every minute (Occurs when seconds reach ":00") Every hour (Occurs when minutes and seconds reach "00:00") Every month (Occurs at 00:00:00 on first day of month) Default
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 See section 6.5 for more detail. Control Register 2 Addr. F Description Control 2 (default)
D7 0
D6 0
D5 /12, 24 Undefined
D4 ADJ or XSTP 1
D3 /CLEN 0
D2 CTFG 0
D1 AAFG 0
D0 BAFG 0
D4 when read is used as ADJ, when write is used as XSTP.
*
/12, 24 /12, 24 time display selection bit. /12, 24 Read/ Write Data 0 1 12-hour time display 24-hour time display Description * Default
See section "Alarm Function" for more detail.
*
ADJ or XSTP ADJ: 30 second adjust bit. Second is adjusted within 122s (within 125s when 32.000kHz crystal is used) from writing operation to ADJ. ADJ Data 0 Write 1 Ordinary operation. Second adjustment. 1) For second range from "00" to "29", second is reset to "00"; 2) For second range from "30" to "59", second is reset to "00" and minute is incremented by 1. Description
XSTP: oscillator halt sensing bit. XSTP Read Data 0 1 Ordinary oscillation. Oscillator halts sensing. Default Description
See section "Oscillation Stop Detection".
PT0150(03/06) 8
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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/CLEN 32-kHz clock output enabled bit. /CLEN Read Data 0 1 Description 32-kHz clock (frequency same as crystal's) output enabled. 32-kHz clock output disabled. Default
*
CTFG CTFG Read Data 0 1 0 Write 1 Description Periodic interrupt output OFF status; /INTA or /INTB= OFF (Hi-z) Read Periodic interrupt output ON status; /INTA or /INTB= "L" A "0" can be written only when the periodic interrupt is in level mode, at which time the /INTA or /INTB pin is set to OFF ("H") status. After a "0" is written, the value still becomes "1" again at the next cycle. Setting prohibited Default Default
See section "Related Registers" for more detail.
*
AAFG, BAFG AAFG,BAFG Data 0 Read 1 Write
Description Alarm register does not match current time Alarm register match current time Default Default
0 /INTA or /INTB pin = OFF (H) 1 Setting prohibited See section "Alarm Function" for more detail. Time Counter
Time digit display (in BCD code): * Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. * Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. * Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. 0 1 2 Description Seconds (default) Minutes (default) Hours (default) D7 0 0 0 D6 D5 D4 D3 D2 D1 D0
S40 S20 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined M40 M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0 H20 or P,/A H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced with correct time; otherwise it will cause the clock counter malfunction.
PT0150(03/06) 9
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Days of the week Counter Addr. 3 Description Days of the week (default) D7 0 D6 0 D5 0 D4 0 D3 0 D2 D1 D0
W4 W2 W1 Undefined Undefined Undefined
"-" indicates write-protected bits. A zero is always read from these bits. The day counter is a divide-by-7 counter that counts from 00 to 01 and up 06 before starting again from 01. The correspondence between days and count values is shown below. Days W4 W2 W1 Day Remark 0 0 0 Sunday 00 h 0 0 1 Monday 01 h 0 1 0 Tuesday 02 h Write / Read 0 1 1 Wednesday 03 h 1 0 0 Thursday 04 h 1 0 1 Friday 05 h 1 1 0 Saturday 06 h Write prohibit 1 1 1 Do not enter a setting for this bit. Calendar Counter The data format is BCD format. * Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. * Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. * Year digits: Range from 00 to 99 and 00, 04, 08, ... , 92 and 96 are counted as leap years. Addr. 4 5 6 Description Days (default) Months (default) Years (default) D7 0 0 D6 0 0 D5 D4 D3 D2 D1 D0
D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined 0 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined
Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Note: Any registered imaginary time should be replaced with correct time; otherwise it will cause the clock counter malfunction. Time Trimming Register Addr. 7 Description Time trimming (default) D7 /XSL 0 D6 F6 0 D5 F5 0 D4 F4 0 D3 F3 0 D2 F2 0 D1 F1 0 D0 F0 0
Note: Time trimming function only adjusts clock timing. Oscillation frequency and 32-kHz clock output is not adjusted.
PT0150(03/06) 10
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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/XSL bit The /XSL bit is used to select frequency of the crystal. /XSL 0 1
Frequency of the crystal (kHz) 32.768 32.000
*
F6 to F0 Implement a higher-precision clock function. See section "Clock Precision Adjustment Function".
Alarm Register See section "Alarm Function" for more details.
*
Alarm_A, Alarm_B Register Alarm_A, Alarm_B can output alarm pulses at the time set as the day-of-the-week, hour, minute (e.g. Monday 7:00 a.m. every day of weeks). Addr. 8 Description Alarm_A: Minute (default) Alarm_A: Hour (default) A B Alarm_A: Day (default) Alarm_B: Minute (default) Alarm_B: Hour (default) D Alarm_B: Day (default) D7 0 0 0 0 0 0 D6 AM40 Undefined 0 AW6 Undefined BM40 Undefined 0 BW6 Undefined D5 AM20 Undefined AH20, or AP,/A Undefined AW5 Undefined BM20 Undefined BH20, or BP,/A Undefined BW5 Undefined D4 D3 D2 D1 D0
AM10 AM8 AM4 AM2 AM1 Undefined Undefined Undefined Undefined Undefined AH10 AH8 AH4 AH2 AH1
9
Undefined Undefined Undefined Undefined Undefined AW4 AW3 AW2 AW1 AW0 Undefined Undefined Undefined Undefined Undefined BM10 BM8 BM4 BM2 BM1 Undefined Undefined Undefined Undefined Undefined BH10 BH8 BH4 BH2 BH1
C
Undefined Undefined Undefined Undefined Undefined BW4 BW3 BW2 BW1 BW0 Undefined Undefined Undefined Undefined Undefined
PT0150(03/06) 11
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Clock Precision Adjustment Function
Adjustment range Adjustment range (ppm) -189.1 to +189.1
*
Adjustment unit (ppm) 3.05 *
Internal timing of adjustment Once every 20 seconds at "00", "20", "40" seconds
note: add or decrement 2 clock pulses every 20s: 2/(32,768x20) = 3.051ppm (or 3.125ppm when 32.000kHz crystal is used).
Adjustment amount and adjustment value Adjustment data Adjustment amount (ppm) Decimal Hexadecimal -189.10 +63 3F h -186.05 +62 3E h -183.00 +61 3D h -9.15 -6.10 -3.05 OFF OFF +3.05 +6.10 +9.15 +183.00 +186.05 +189.10 OFF OFF ... PT0150(03/06) 12 ... ... +4 +3 +2 +1 0 -1 -2 -3 -60 -61 -62 -63 -64 ... 04 h 03 h 02 h 01 h 00 h 7F h 7E h 7D h 44 h 43 h 42 h 41 h 40 h ... ...
bit 6 F6 0 0 0 ... 0 0 0 0 0 1 1 1 ... 1 1 1 1 1
bit 5 F5 1 1 1 ... 0 0 0 0 0 1 1 1 ... 0 0 0 0 0
bit 4 F4 1 1 1 ... 0 0 0 0 0 1 1 1 ... 0 0 0 0 0
bit 3 F3 1 1 1 ... 0 0 0 0 0 1 1 1 ... 0 0 0 0 0
bit 2 F2 1 1 1 ... 1 0 0 0 0 1 1 1 ... 1 0 0 0 0
bit 1 F1 1 1 0 ... 0 1 1 0 0 1 1 0 ... 0 1 1 0 0
bit 0 F0 1 0 1 ... 0 1 0 1 0 1 0 1 ... 0 1 0 1 0
Examples: (1) Setting time forward Adjust (advance) the clock precision when FOUT clock output is 32767.7 Hz *Determine the current amount of variance (32767.7 -32768) / 32768 = -9.16 x 10 -6 *[ 32768 ] = Reference values *Calculate the optimum adjustment data (decimal value) relative to the current variance. Adjustment data = variance / adjustment resolution = -9.16 / 3.05 -3 *Calculate the setting adjustment data (hexadecimal) Setting adjustment data = 128 -3 (80 h - 03h) = 125 (7D h) (2) Setting time backward Adjust (set back) the clock precision when FOUT clock output is 32768.3 Hz *Determine the current amount of variance (32768.3 -32768) / 32768 = +9.16 x 10 -6 *Calculate the optimum adjustment data (decimal value) relative to the current variance. Adjustment data = (variance / adjustment resolution) + 1 = (+9.16 / 3.05) + 1 +4 *Add 1 since reference value is 01h *Calculate the setting adjustment data (hexadecimal) Setting adjustment data = 04 h
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Alarm Function
These part no have Alarm A and Alarm B functions which can all output alarm pulses at the preset days of the week, hours and minutes. Related register
Addr.
1 2 3 8 9 A B C D E F
Function
Minutes Hours Days of the week Alarm_A: Minute Alarm_A: Hour Alarm_A: Day Alarm_B: Minute Alarm_B: Hour Alarm_B: Day Control 1 Control 2
Bit 7
AALE -
Bit 6
M40 AM40 AW6 BM40 BW6 BALE -
Bit 5
M20 H20 or P, /A AM20 AH20 or AP, /A AW5 BM20 BH20 or BP, /A BW5 SL2 /12, 24
Bit 4
M10 H10 AM10 AH10 AW4 BM10 BH10 BW4 SL1 ADJ or XSTP
Bit 3
M8 H8 AM8 AH8 AW3 BM8 BH8 BW3 TEST CLEN
Bit 2
M4 H4 W4 AM4 AH4 AW2 BM4 BH4 BW2 CT2 CTFG
Bit 1
M2 H2 W2 AM2 AH2 AW1 BM2 BH2 BW1 CT1 AAFG
Bit 0
M1 H1 W1 AM1 AH1 AW0 BM1 BH1 BW0 CT0 BAFG
AALE, BALE: This bit is used to set up the Alarm A/B function (to generate alarms matching day, hour, or minute settings). AALE, BALE Data Description 0 Alarm_A (Alarm_B) correspondence action invalid Default Read / Write 1 Alarm_A (Alarm_B) correspondence action valid * When using the Alarm A (or B) function, first set this AALE (or BALE) bit value as "0" to stop the function. Next, set the day, hour, minute, and set the AAFG (or BAFG) bit to 0. Finally, set "1" to the AALE (or BALE) bit to set the Alarm A (or B) function as valid. The reason for first setting the AALE (or BALE) bit value as "0" is to prevent /INTB or /INTA = "L" output in the event that a match between the current time and alarm setting occurs while the alarm setting is still being made.
*
PT0150(03/06) 13
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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AAFG, BAFG: These bits are valid only when the AALE, BALE bits value are "1". When a match occurs between the Alarm A or Alarm B setting and the current time, the AAFG or BAFG bit value becomes "1" approximately 61 s afterward. (There is no effect when the AALE or BALE bit becomes "0".) The /INTB or /INTA = "L" status that is set at this time can be set to OFF by writing a "0" to these bits. AAFG,BAFG Data Description 0 Alarm register does not match current time Default Read 1 Alarm register match current time Write 0 1 /INTA or /INTB pin = OFF (H) Setting prohibited Default
*
SL2, SL1 (PT7C4372A only): Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may be output to the /INTA or /INTB pins selectively by SL1 and SL2. SL2 0 0 1 1 SL1 0 1 0 1 Description Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB. Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB. Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB. Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB. Default
*
/12, 24: This bit is used to select between 12-hour clock operation and 24-hour clock operation. 12/24 Description Time 24-hour clock 00 01 02 03 04 05 06 07 08 09 10 11 12-hour clock 12 ( AM 12) 01 ( AM 01 ) 02 ( AM 02 ) 03 ( AM 03 ) 04 ( AM 04 ) 05 ( AM 05 ) 06 ( AM 06 ) 07 ( AM 07 ) 08 ( AM 08 ) 09 ( AM 09 ) 10 ( AM 10 ) 11 ( AM 11 ) 24-hour clock 12 13 14 15 16 17 18 19 20 21 22 23 12-hour clock 32 ( PM 12 ) 21 ( PM 01 ) 22 ( PM 02 ) 23 ( PM 03 ) 24 ( PM 04 ) 25 ( PM 05 ) 26 ( PM 06 ) 27 ( PM 07 ) 28 ( PM 08 ) 29 ( PM 09 ) 30 ( PM 10 ) 31 ( PM 11 )
0
12-hour time display
1
24-hour time display
* Be sure to select between 12-hour and 24-hour clock operation before writing the time data.
PT0150(03/06) 14
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Examples: Alarm_A/B: Day-of-the-week Alarm_A/B: Hour Alarm_A/B: Minute Sun. Mon. Tue. Wed. Thu. Fri. Sat. 24-hour 12-hour Minute AW0 AW1 AW2 AW3 AW4 AW5 AW6 (Hexadecimal) (Hexadecimal) (Hexadecimal) AM 00:00 every day 1 1 1 1 1 1 1 00 00 00 AM 01:30 every day 1 1 1 1 1 1 1 01 01 30 AM 11:59 on Mon. 0 1 0 0 0 0 0 11 11 59 PM 00:00 on Mon. to Fri. 0 1 1 1 1 1 0 12 32 00 PM 01:30 on Sun. 1 0 0 0 0 0 0 13 21 30 PM 11:59 on Mon, Wed. 0 1 0 1 0 0 0 23 31 59 Alarm time settings WAFG, DAFG and /INTA, /INTB output
61us (approx) AAFG (BAFG) bit
61us (approx)
/INTA or /INTB pins (/INTB only for PT7C4372A) Set AAFG (BAFG) to 0 Matched alarm time Matched alarm time Set AAFG (BAFG) to 0 Matched alarm time
PT0150(03/06) 15
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Periodic Interrupt Function
Periodic interrupt output can be obtained via PT7C4372B: /INTA pin, PT7C4372A: /INTA or /INTB pin. Select among five periodic-cycle settings: 2 Hz (once per 0.5 seconds), 1 Hz (once per second), 1/60 Hz (once per minute), 1/3600 Hz (once per hour), or monthly (on the 1 st of each month). Select between two output waveforms for periodic interrupts: an ordinary pulse waveform (2 Hz or 1 Hz) or a waveform (every second, minute, hour, or month) for CPU-level interrupts that can support CPU interrupts. A polling function is also provided to enable monitoring of pin states via registers. Related registers Period interrupt output via PT7C4372A: /INTA, /INTB; PT7C4372B: /INTA Addr. Function Bit 7 Bit 6 Bit 5 Bit 4 E F Control 1 Control 2 AALE BALE SL2 /12, 24 SL1 ADJ or XSTP
Bit 3 TEST /CLEN
Bit 2 CT2 CTFG
Bit 1 CT1 AAFG
Bit 0 CT0 BAFG
*
SL2, SL1 (PT7C4372A only) Interrupt output select bits. Two alarm pulses (Alarm_A and alarm_B), periodic interrupt output (INT), 32kHz clock pulses may be output to the /INTA or /INTB pins selectively by SL1 and SL2. SL2 0 0 1 1 SL1 0 1 0 1 Description Output Alarm_A, Alarm_B, INT to the /INTA. Output 32kHz clock pulses to /INTB. Output Alarm_A, INT to the /INTA. Output 32kHz clock pulses, Alarm_B to /INTB. Output Alarm_A, Alarm_B to the /INTA. Output 32kHz clock pulses, INT to /INTB. Output Alarm_A to the /INTA. Output 32kHz clock pulses, Alarm_B, INT to /INTB. Default
*
CTFG: During a read operation, this bit indicates the /INTA or /INTB pin's periodic interrupt output status. This status can be set as OFF by writing a "0" to this bit when /INTA or /INTB = " H". CTFG Data Description 0 Read 1 0 Write 1 Periodic interrupt output OFF status; /INTA or /INTB= OFF (Hi-z) Read Periodic interrupt output ON status; /INTA or /INTB= "L" A "0" can be written only when the periodic interrupt is in level mode, at which time the /INTA or /INTB pin is set to OFF ("H") status. After a "0" is written, the value still becomes "1" again at the next cycle. Setting prohibited Default Default
PT0150(03/06) 16
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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CT2, CT1, CT0: Periodic interrupt output select bits. CT2 0 0 0 0 1 1 1 1 CT1 0 0 1 1 0 0 1 1 CT0 0 1 0 1 0 1 0 1 Wave Form Mode Pulse Pulse Level Level Level Level Description Cycle / Falling Timing Off ("H") Default Fixed at "L" 2Hz (duty 50%) 1Hz (duty 50%) Every second (synchronized with second count up) Every minute (Occurs when seconds reach ":00") Every hour (Occurs when minutes and seconds reach "00:00") Every month (Occurs at 00:00:00 on first day of month)
Mode-specific output waveforms 1) Pulse mode: Output 2 Hz, 1Hz clock pulses.
CTFG bit
/INTA or /INTB pins (/INTB only for PT7C4372A) Approx. 92us (32.768kHz crystal is used) 94us (32.000kHz crystal is used) Counting up of seconds Since counting up of seconds and the falling edge has a time lag of approx. 92us (at 32.768kHz) (Approx. 94us when 32.000kHz is used), time with apparently approx. one second of delay from time of the real-time clock may be read when time is read in synchronization with the falling edge of output.
PT0150(03/06) 17
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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2) Level mode: One second, one minute or one month may be selected for an interrupt cycle. Counting up of seconds is matched with falling edge of interrupt output.
CTFG bit
/INTA or /INTB pins (/INTB only for PT7C4372A)
Write 0 to CTFG Second count-up Second count-up
Write 0 to CTFG Second count-up
3) When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds. Pulse mode: The period during which the output pulse is low can be adjusted backward or forward up to 3.784ms (3.875ms when 32.000kHz crystal is used). For example, the duty for the 1-Hz setting can be adjusted 0.3784% (or 0.3875% when 32.000kHz crystal is used) from 50%. Level mode: a one-second period can be adjusted backward or forward up to 3.784 ms (3.875ms when 32.000kHz crystal is used).
PT0150(03/06) 18
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Various Detection Function
PT7C4372A/B detection function includes oscillation stop detection as well as reporting of detection results in corresponding bits of Control 2 register. The status of the power supply, oscillation circuit, and clock can be confirmed by checking these results. *Note with caution that detection functions may not operate correctly when power flickers occur. Related register Addr. F Function Control 2 Bit 7 Bit 6 Bit 5 /12, 24 Bit 4 ADJ or XSTP Bit 3 /CLEN Bit 2 CTFG Bit 1 AAFG Bit 0 BAFG
Oscillation stop detection When read control register 2 bit 4, this bit is as XSTP bit sensing oscillator halt. This bit is as 30 second adjust bit when write. XSTP Read Data 0 1 Ordinary oscillation. Oscillator halts sensing. Default Description
This bit senses the oscillator halt. When oscillation is halted after initial power on from 0V or drop in supply voltage, the bit is set to "1" and remains to be "1" after it is restarted. This bit may be used to judge validity of clock and calendar count data after power on or supply voltage drop. When this bit is set to "1", the Time Trimming register, Control 1 register, /CLEN and TEST bits are reset to "0". /INTA will stop output and the /INTB will output 32-kHz clock pulses. This bit is set to "0" by setting the control register 2 during ordinary oscillation.
PT0150(03/06) 19
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Reading / Writing Data via the I2C Bus Interface
Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. System Configuration All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the Vcc line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed). Fig 4. System configuration
Vcc RP RP
SDA SCL
Master MCU
Slave RTC
Other Peripheral Device
Note: When the master is one, the MCU is ready for driving SCL to "H" and RP of SCL may not required.
PT0150(03/06) 20
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Starting and Stopping I2C Bus Communications Fig 5. Starting and stopping on I2C bus
1) START condition, repeated START condition, and STOP condition a) START condition SDA level changes from high to low while SCL is at high level b) STOP condition SDA level changes from low to high while SCL is at high level c) Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. 2) Caution points a) The master device always controls the START, RESTART, and STOP conditions for communications. b) The master device does not impose any restrictions on the timing by which STOP conditions affect transmissions, so communications can be forcibly stopped at any time while in progress. (However, this is only when this RTC module is in receiver mode (data reception mode = SDA released). c) When communicating with this RTC module, the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 0.5 seconds. (A RESTART condition may be sent between a START condition and STOP condition, but even in such cases the series of operations from transmitting the START condition to transmitting the STOP condition should still occur within 0.5 seconds.) If this series of operations requires 0.5 to 1.0 seconds or longer, the I 2 C bus interface will be automatically cleared and set to standby mode by this RTC module's bus timeout function. Note with caution that both write and read operations are invalid for communications that occur during or after this auto clearing operation. (When the read operation is invalid, all data that is read has a value of "1"). Restarting of communications begins with transfer of the START condition again. d) When communicating with this RTC module, wait at least 1.3 s between transferring a STOP condition (to stop communications) and transferring the next START condition (to start the next round of communications). (If any carries occur in the time data during this communication period, corrections are made during this period.) Fig 6. Interval between start and stop
1.3
PT0150(03/06) 21
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Data Transfers and Acknowledge Responses during I2C-BUS Communication 1) Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. (However, the transfer time must be no longer than 0.5 seconds and access to the Address Dh (Reserved) register is prohibited.) The address auto increment function operates during both write and read operations. After address Fh, increment goes to address 0h. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition. 2) Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
SCL from Master
1
2
8
9
SDA from transmitter (sending side)
Release SDA Low active ACK signal
SDA from receiver (receiving side)
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master.
PT0150(03/06) 22
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Slave Address The I 2 C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. This RTC's slave address is [ 0110 010 ]. An R/W bit ("*" above) is added to each 7-bit slave address during 8-bit transfers. Table Slave address R / W bit Transfer data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read 65 h 1 (= Read) 0 1 1 0 0 1 0 Write 64 h 0 (= Write)
I2C Bus's Basic Transfer Format
S
Start indication
P
Stop indication
A
RTC Acknowledge
Sr
Restart indication
A
Master Acknowledge
1) Write via I2C bus
S 0
Start
Slave address (7 bits) 1 1 0 0 1 0
write A
0
A C K
Addr. setting 0h~Fh
Transfer mode 0 10 0 0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
A
P
Slave address + write specification
Address + transfer mode specification 1) Specifies the write start address; 2) Specifies the write mode (=0h fixed)
A C K
Write data
A C K
Stop
PT0150(03/06) 23
Ver: 3
Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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2) Read via I2C bus a) Standard read
S 0
Start
Slave address (7 bits) 1 1 0 0 1 0
write A
0
A C K
Addr. setting 0h~Fh
Transfer mode 0 0 0 0
A
Slave address + write specification
Address + transfer mode specification 1) Specifies the write start address; 2) Specifies the write mode (=0h fixed)
A C K
Sr 0
Restart
Slave address (7 bits) 1 1 0 0 1 0
Read
A
bit
bit
bit
bit
bit
bit
bit
bit
1
A C K
7
6
5
4
3
2
1
0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
/A
P
Slave address + read specification indicating next byte will be read.
Data read (1) Data is read from the specified start address and address auto increment.
A C K
Data read (2) Address auto increment to set the address for the next data to be read.
N O A C K
Stop
b)
Simplified read
Addr. setting 0h~Fh
S 0
Start
Slave address (7 bits) 1 1 0 0 1 0
write A
Transfer mode 0 1 0 0
A
0
A C K
Slave address + write specification
Address + transfer mode specification 1) Specifies the write start address; 2) Specifies the write mode (=4h fixed)
A C K
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
/A
P
Data read (1) Data is read from the specified start address and address auto increment.
A C K
Data read (2) Address auto increment to set the address for the next data to be read.
N O A C K
Stop
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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c) Simplified read with no start address indicating Only when reading from address Fh (Fh 0h 1h 2h, etc.), a read operation can be performed without specifying the read start address or the transfer mode.
S 0
Start
Slave address (7 bits) 1 1 0 0 1 0
Read
A
bit
bit
bit
bit
bit
bit
bit
bit
1
A C K
7
6
5
4
3
2
1
0
A
bit
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
0
/A
P
Slave address + read specification indicating next byte will be read.
Data read (1) Data is read from the specified start address and address auto increment.
A C K
Data read (2) Address auto increment to set the address for the next data to be read.
N O A C K
Stop
Note: The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. (However, the transfer time must be no longer than 0.5 seconds.)
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Configuration of Oscillating Circuit and Timing Trimming
Configuration of Oscillating Circuit
The oscillation circuit is driven at a constant voltage of about 1.2V relative to the GND level. Consequently, it generates a wave form having a peak -to-peak amplitude of about 1.2V on the positive side of the GND Level.
PT7C4372A/B
Typical external device: Crystal: 32.768kHz (RL = 30k typ., CL = 6 to 8pF) Typical value of internal devices: RF 150M (typ) RD 60k (typ) CG, CD 10pF (Typ)
Consideration on Crystal Oscillator Basic characteristics of a crystal oscillator includes R1 (equivalent series resistance: ease of oscillation) and CL (load capacitance: rank of center frequency). RL = TYP of 30k, CL = 6 to 8pF is recommended for the PT7C4372A/B. Confirm recommended values to the manufacturer of the crystal oscillator used. Considerations in Mounting Components Surrounding Oscillating Circuit 1) Mount the crystal oscillators in the closest possible position to the IC. 2) Avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with "A" in the above figure). 3) Apply the highest possible insulation resistance between the OSCOUT pin and the PCB. 4) Avoid using any long parallel line to wire the OSCIN and OSCOUT pin. 5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt. Other Relevant Considerations 1) When applying an external input of clock pulses (32.768kHz or 32.000kHz) to the OSCIN pin and the PCB. DC coupling : prohibited due to mismatching of mismatching of levels. AC coupling : permissible except that unpredictable results may occur in oscillator halt sensing due to Possible sensing errors caused by noises, etc. Avoid using the oscillator output of the PT7C4372A/B (from the OSCOUT pin) to drive any other IC for the purpose of ensuring stable oscillation.
2)
PT0150(03/06) 26
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Measurement of Oscillation Frequency
PT7C4372A/B
*1. Clock pulse of 32.768kHz or 32.000kHz is output from the /INTB output pin on powering on (XSTP is set to 1). *2. Use a frequency counter having at least 6 digits (7 digits or more recommended). *3. Pull-up the /INTB output pin to Vcc for the 4372A.
/INTB (FOUT) GND
*4. /INTB applies to the 4372A, and FOUT applies to the 4372B. The 4372B does not need pull-up resistor.
Oscillation Frequency Adjustment please refer to page 12, Clock Precision Adjustment Function.
PT0150(03/06) 27
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Specifications
Maximum Ratings
Storage Temperature...................................................................................................................-65oCto +150oC Ambient Temperature with Power Applied.........................................................................-40oCto +85oC Supply Voltage to Ground Potential (Vcc to GND) ........................................................-0.3V to +6.5V DC Input (All Other Inputs except Vcc & GND).............................................................-0.3V to (Vcc+0.3V) DC Output Voltage (SDA, /INTA, /INTB pins).................................................................-0.3V to +6.5V DC Output Current (FOUT).....................................................................................................-0.3V to (Vcc+0.3V) Power Dissipation.........................................................................................................................320mW (depend on package)
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol VCC VCLK VPUP TA Power voltage Clock voltage Applied voltage when OFF (SCL, SDA, /INTA, /INTB pins) Operating temperature Description Min 2 1.45 -0.3 -40 Type Max 5.5 5.5 5.5 85 C V Unit
Frequency Characteristics
Symbol f / f f/V Top tSTA fa Description Frequency tolerance Frequency voltage characteristics Frequency temperature characteristics Oscillation start up time Aging Condition TA = +25C Vcc = 3.0 V TA = +25C Vcc = 2 V to 5 V TA = -10C to +70C, Vcc = 3.0 V; +25C reference TA = +25C Vcc = 3 V TA = +25C VCC=3.0 V; first year Rating Stability AC: 0 5 2 Max. +10 / -120 3 Max. 5 Max. Unit x 10 -6 x 10 -6 / V x 10 -6 s x 10 -6 / year
PT0150(03/06) 28
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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DC Electrical Characteristics
Unless otherwise specified, GND = 0 V, VCC = 3 V, TA = -40 C to +85 C Sym. ICC VIL VIH IOH IOL IIL IOZ Item Current consumption Low-level input voltage High-level input voltage High-level output current Low-level output current Input leakage current Output current when OFF Vcc SCL, SDA, FOE FOUT 1) FOUT 1) /INTA,/INTB SDA SCL SDA, /INTA,/INTB OSCIN OSCOUT VOH = VCC -0.5 VOL = 0.4 VOL = 0.6 VI = 5.5V or GND, VCC = 5.5V VO = 5.5V or GND, VCC = 5.5V Pin Condition SCL, SDA=VCC, others float VCC: 3V -0.3 0.8VCC -0.3 0.5 1.0 6.0 -1 -1 10 10 Min Typ 0.5 Max 1.2 0.2VCC 6.0 0.2VCC Unit A V V mA mA 1 1 A A pF pF
CG2) Internal oscillation CD2) capacitance 1) Only PT7C4372B has FOUT pin. 2) Only reference for design.
PT0150(03/06) 29
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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AC Electrical Characteristics
Sym VHM VHL Description Rising and falling threshold voltage high Rising and falling threshold voltage low Value 0.8 VCC 0.2 VCC Unit V V
Signal VHM VLM
tf
tr
*Unless otherwise specified: GND = 0 V, VCC = 2 V to 5.5 V, TA = -40 C to +85 C, CL = 50 pF Symbol Item Min. Typ. fSCL tSU;STA tHD;STA tSU;DAT tHD;DAT1 tHD;DAT2 tSU;STO tBUF tLOW tHIGH tr tf tSP* tD SCL clock frequency START condition set-up time START condition hold time Data set-up time (RTC read/write) Data hold time (RTC write) Data hold time (RTC read) STOP condition setup time Bus idle time between a START and STOP condition When SCL = "L" When SCL = "H" Rise time for SCL and SDA Fall time for SCL and SDA Allowable spike time on bus Duration of staring to stopping 0.6 0.6 200 35 0 0.6 1.3 1.3 0.6
Max. 400
Unit kHz s s ns ns s s s s s
0.3 0.3 50 0.5
s s ns s
* Note: only reference for design
S SCL tLOW fSCL tSU;DAT tHIGH Sr tHD;STA tSP P tSU;STA
tBUF tSU;STO tHD;STA
SDA tHD;STA tHD;DAT tD S Sr Start condition Restart condition P Stop condition tSU;STA
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Mechanical Information
L/LE (8-pin TSSOP) 8
.169 .177
4.3 4.5
1 .114 .122 2.90 3.10 .047 max 1.20 SEATING PLANE X.XX X.XX 0.45 0.75 .020 .030 .004 .008 0.09 0.20
.252 BSC 6.4 BSC
.0256 BSC 0.65 0.19 0.30
.002 .006
0.05 0.15
DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS
.007 .012
Note: Maximum package length and width dimensions do not include moldflash protrusions or gate burrs, which shall not exceed 0.006 inch per side(Ref: JEDEC MO-153AA).
PT0150(03/06) 31
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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W/WE (8-pin SOP) 8
.149 3.78 .157 3.99
1 .189 .196 4.80 5.00
.0099 0.25 x 45o .0196 0.50 0-8o 0.40 1.27 .016 .050 .0075 .0098 0.19 0.25
.016 .026 0.406 0.660 REF .050 BSC 1.27
.053 .068
1.35 1.75 SEATING PLANE
.2284 .2440 5.80 6.20
.0040 .0098 .013 0.330 .020 0.508
0.10 0.25
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012 AA
PT0150(03/06) 32
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Data Sheet PT7C4372A/4372B Real-time Clock Module (I2C Bus)
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Notes
Pericom Technology Inc.
Email: support@pti.com.cnWeb Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Asia Pacific:
U.S.A.:
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
PT0150(03/06) 33
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